In the manufacturing of integrated circuits, the sizes of integrated circuit devices are scaled down increasingly. For example, Complementary Metal-Oxide-Semiconductor (CMOS) Image Sensor (CIS) chips have increasingly smaller pixel sizes. Accordingly, the requirement in the DC and noise performance of the CIS chips becomes increasingly stricter. Implant isolation regions formed by well implantation are thus replacing the conventional Shallow Trench Isolation (STI) regions to isolate devices. With the formation of the implant isolation regions using implantation rather than STI regions, the damage to silicon surfaces caused by the formation of the STI regions is eliminated.
The implant isolation regions are formed by implanting an impurity to portions of a substrate, which portions surround the active regions of the integrate circuit devices that are to be isolated. It is difficult to control the accuracy in the overlay of the components of the integrated circuit devices with the implant isolation regions. If the gate electrodes are misaligned to the implant isolation regions, gate electrodes may not be able to fully separate the channel between the source and drain regions of the devices, forming a leakage path. Under high voltage application to a gate electrode over the implant isolation region, a parasitic transistor may develop.